[CONTRACT] UVM Verification Engineer
Austria - Villach
On-Site
Contract
Job Description
Job Title: UVM Verification Engineer
Location: Austria
Duration: 6 months
Extension: Yes
Start: ASAP
Remote: Yes
For our client in Austria, we are looking for a Senior Verification Engineer to join their Digital Mixed-Signal Verification team. The role will be responsible to their Austria site but work can be performed remotely.
This role will require an engineer to have strong knowledge in Functional Verification for Digital and Mixed-Signal blocks.
Skills
- Functional Verification
- SystemVerilog
- UVM
- Experience in mixed signal IPs, e.g. ADCs, PLLs, power converters, etc.
Preferred Skills
- Xcelium
- Vmanager
- Certitude
- Jira
Job Title: UVM Verification Engineer
Location: Austria
Duration: 6 months
Extension: Yes
Start: ASAP
Remote: Yes
For our client in Austria, we are looking for a Senior Verification Engineer to join their Digital Mixed-Signal Verification team. The role will be responsible to their Austria site but work can be performed remotely.
This role will require an engineer to have strong knowledge in Functional Verification for Digital and Mixed-Signal blocks.
Skills
- Functional Verification
- SystemVerilog
- UVM
- Experience in mixed signal IPs, e.g. ADCs, PLLs, power converters, etc.
Preferred Skills
- Xcelium
- Vmanager
- Certitude
- Jira
19003ua6
| Digital IC Design / Verification: | Verification |
