Analog Mixed Signal IC Layout Engineer
Spain - Madrid
On-Site
Permanent
My client specializes in high-speed optical communication, developing gigabit and multi-gigabit transceivers for automotive, industrial, and home networking applications.
As part of their growth plans, they are seeking an experienced Analog Mixed Signal IC Layout Designer to join their Spanish team.
TASKS & RESPONSABILITIES
* Layout of the analog and mixed signal blocks that are embedded in the system (ADC, DAC, PLL, TIAs, VCSEL drivers, SerDes, PLLs, VCOs…)
* Generation of the layout block placing from a schematic design, planning of the layout, pin position and boundary definition.
* Physical verification (DRC and LVS) of the layout.
* Chip-level analog back-end process.
* Generation of extracted netlist and pre-annotation of significant layout parasitic components at schematic level for verification.
* Reliability analysis verification of the layout (electromigration, voltage drop, etc.)
* Back-end process for system-level integration: dummy filing, ERC, ESD and latch-up prevention rules, etc.
* Generation of LEF and abstracts of the AMS blocks for digital co-integration.
* Cooperation with layout engineers for flow optimization and double reviewing process implementation.
* Collaboration and cooperation with design engineers to align on system-level requirements and critical sections of the layout.
* Continuous improvement of design and, specifically, layout flow, to optimize resources and execution time.
* Implementation of automatization scripts for layout optimization and reducing schematicto-layout process.
* Generation of guidelines for design and verification engineers to improve layout execution.
* Research on new tools or solutions for layout tasks.
REQUIREMENTS
* MSc/PhD in Electronics, Electrical, Computer Engineering or relevant field.
* At least 3 years of experience in similar tasks.
DESIRABLE COMPETENCES
Knowledge:
* Experience in delivering successful design in silicon, preferably in high-speed system communication systems.
* Experience on designing full-custom analog IP blocks in nanometric CMOS planar technology (65/28 nm) and CMOS FinFET (16/12 nm or below), as well as with analog and mixed-signal IC EDA tools, such as Cadence or Synopsys.
* Knowledge of the complete design flow (from schematic to full verification at extracted level) of the analog and mixed-signal blocks in nanometric CMOS processes.
* Good knowledge of full-custom analog layout techniques, including the ability to manage and review the work of others.
* Excellent written and verbal English communication skills.
Personal profile:
* Dynamic person with motivation and taste for his work, analytical, organized and with high personal motivation and ready to integrate into a young team, and very dynamic.
If you are keen in learning more about this opportunity, then get in touch!
As part of their growth plans, they are seeking an experienced Analog Mixed Signal IC Layout Designer to join their Spanish team.
TASKS & RESPONSABILITIES
* Layout of the analog and mixed signal blocks that are embedded in the system (ADC, DAC, PLL, TIAs, VCSEL drivers, SerDes, PLLs, VCOs…)
* Generation of the layout block placing from a schematic design, planning of the layout, pin position and boundary definition.
* Physical verification (DRC and LVS) of the layout.
* Chip-level analog back-end process.
* Generation of extracted netlist and pre-annotation of significant layout parasitic components at schematic level for verification.
* Reliability analysis verification of the layout (electromigration, voltage drop, etc.)
* Back-end process for system-level integration: dummy filing, ERC, ESD and latch-up prevention rules, etc.
* Generation of LEF and abstracts of the AMS blocks for digital co-integration.
* Cooperation with layout engineers for flow optimization and double reviewing process implementation.
* Collaboration and cooperation with design engineers to align on system-level requirements and critical sections of the layout.
* Continuous improvement of design and, specifically, layout flow, to optimize resources and execution time.
* Implementation of automatization scripts for layout optimization and reducing schematicto-layout process.
* Generation of guidelines for design and verification engineers to improve layout execution.
* Research on new tools or solutions for layout tasks.
REQUIREMENTS
* MSc/PhD in Electronics, Electrical, Computer Engineering or relevant field.
* At least 3 years of experience in similar tasks.
DESIRABLE COMPETENCES
Knowledge:
* Experience in delivering successful design in silicon, preferably in high-speed system communication systems.
* Experience on designing full-custom analog IP blocks in nanometric CMOS planar technology (65/28 nm) and CMOS FinFET (16/12 nm or below), as well as with analog and mixed-signal IC EDA tools, such as Cadence or Synopsys.
* Knowledge of the complete design flow (from schematic to full verification at extracted level) of the analog and mixed-signal blocks in nanometric CMOS processes.
* Good knowledge of full-custom analog layout techniques, including the ability to manage and review the work of others.
* Excellent written and verbal English communication skills.
Personal profile:
* Dynamic person with motivation and taste for his work, analytical, organized and with high personal motivation and ready to integrate into a young team, and very dynamic.
If you are keen in learning more about this opportunity, then get in touch!
19003u8p
| Analog / Mixed-Signal / RFIC: | IC Layout |
