[CONTRACT] UVM Verification Engineer
Belgium - 1050
Contract
Job Description
Job Title: UVM Verification Engineer
Job Type: Contract
Duration: 6 months initial plus extension possibility
Location: Brussels, Belgium
Remote: 2 weeks ramp-up on-site followed by remote working
Start: ASAP
Required Skills:
You have at least 10 years of proven experience in designing and verifying digital circuits, ideally in the field of Image Sensors.
Knowledge of the following is required:
- UVM
- SystemVerilog for RTL design and verification (SVA)
- Python scripting language.
- EDA Tools: Xcelium, SpyGlass (Lint, CDC), Synopsys DC
- Version Control SW, eg GIT or SVN.
- You have a strong working knowledge of English.
Knowledge of the following is an asset:
- Design experience in an automotive context (IATF16949, ISO26262).
- Analog Mixed Signal verification.
- Formal verification.
- Continuous Integration tools, eg Jenkins or Gitlab.
- JIRA.
- Working knowledge of Japanese.
Job Title: UVM Verification Engineer
Job Type: Contract
Duration: 6 months initial plus extension possibility
Location: Brussels, Belgium
Remote: 2 weeks ramp-up on-site followed by remote working
Start: ASAP
Required Skills:
You have at least 10 years of proven experience in designing and verifying digital circuits, ideally in the field of Image Sensors.
Knowledge of the following is required:
- UVM
- SystemVerilog for RTL design and verification (SVA)
- Python scripting language.
- EDA Tools: Xcelium, SpyGlass (Lint, CDC), Synopsys DC
- Version Control SW, eg GIT or SVN.
- You have a strong working knowledge of English.
Knowledge of the following is an asset:
- Design experience in an automotive context (IATF16949, ISO26262).
- Analog Mixed Signal verification.
- Formal verification.
- Continuous Integration tools, eg Jenkins or Gitlab.
- JIRA.
- Working knowledge of Japanese.
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| Digital IC Design / Verification: | Verification |
