Principal Engineer / Expert in Formal Verification
France - Grenoble
Permanent
We have had an exciting opportunity become available for a Principal Engineer / Expert in Formal Verification in Grenoble / Paris, France.
ROLE: Principal Engineer / Expert in Formal Verification
LOCATION: Grenoble or Paris, France
DURATION: Permanent
SALARY: Negotiable
Overview:
Join a leading research team dedicated to advancing formal verification methods in chip design and system-level verification. We are expanding and looking for skilled engineers to drive innovative projects in Paris or Grenoble.
Job Summary:
We seek two experienced engineers for the roles of Principal Engineer and Expert in Formal Verification. Ideal candidates will possess deep expertise in formal methods applied to chip design and verification, including EDA tools, and system design.
Responsibilities:
• Develop and apply formal verification techniques for chip design and EDA tools, as well as system design.
• Collaborate with interdisciplinary teams to integrate formal methods into design processes.
• Research and implement innovative formal verification solutions for enhanced efficiency and scalability.
• Provide technical leadership, mentoring junior engineers, and driving strategic tool development.
• For Paris roles, take a leadership position in establishing and growing the local team.
Required experience:
• Extensive experience in formal verification, especially in chip design and EDA tools.
• Strong industrial background and proficiency in hardware description languages (HDLs).
• Advanced knowledge of formal methods like model checking and symbolic execution.
• PhD in computer science, formal methods, or a related field.
• Excellent leadership and problem-solving skills, with a collaborative approach.
Take a leading role in shaping our Paris presence or contribute to our established Grenoble team.
Engage in groundbreaking projects that influence chip design and system verification.
Collaborate with experts in formal verification methods and applications.
If you could be suitable for this position, please send your CV tee@microtech-global.com
ROLE: Principal Engineer / Expert in Formal Verification
LOCATION: Grenoble or Paris, France
DURATION: Permanent
SALARY: Negotiable
Overview:
Join a leading research team dedicated to advancing formal verification methods in chip design and system-level verification. We are expanding and looking for skilled engineers to drive innovative projects in Paris or Grenoble.
Job Summary:
We seek two experienced engineers for the roles of Principal Engineer and Expert in Formal Verification. Ideal candidates will possess deep expertise in formal methods applied to chip design and verification, including EDA tools, and system design.
Responsibilities:
• Develop and apply formal verification techniques for chip design and EDA tools, as well as system design.
• Collaborate with interdisciplinary teams to integrate formal methods into design processes.
• Research and implement innovative formal verification solutions for enhanced efficiency and scalability.
• Provide technical leadership, mentoring junior engineers, and driving strategic tool development.
• For Paris roles, take a leadership position in establishing and growing the local team.
Required experience:
• Extensive experience in formal verification, especially in chip design and EDA tools.
• Strong industrial background and proficiency in hardware description languages (HDLs).
• Advanced knowledge of formal methods like model checking and symbolic execution.
• PhD in computer science, formal methods, or a related field.
• Excellent leadership and problem-solving skills, with a collaborative approach.
Take a leading role in shaping our Paris presence or contribute to our established Grenoble team.
Engage in groundbreaking projects that influence chip design and system verification.
Collaborate with experts in formal verification methods and applications.
If you could be suitable for this position, please send your CV tee@microtech-global.com
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| Digital IC Design / Verification: | Verification |
