Verification Engineer
Netherlands - Delft
Permanent
Job Title: Digital Verification Engineer
Position: Permanant
Location: Delft, Netherlands
Salary Range: 60K – 75K EUR dependant on experience
Client Information:
Our client is on a mission to conquer the high-power consumption challenges in Global Navigation Satellite Systems
and IoT sensors. With a great team of over 25 individuals, scaling to 40 next year, hosting more than 12 nationalities,
we've achieved the impossible - the world's lowest power GNSS chipset. Now, we're on the verge of unleashing our
game-changing digital RF technology product, ready to flood the market with millions of annual shipments.
Responsibilities:
• You will work in our offices in Delft.
• You are responsible for ASIC verification, System Verilog, and UVM.
• You will be responsible for the simulation and verification of digital block implementation in RTL for various
functions, including control state machine digital processing (DSP), and multiple clock domain interface
management.
• You will be responsible for the post-layout simulation of complex mixed-signal SoC.
• As a Digital ASIC Verification engineer you will develop test benches and test cases for block-level functional
verification.
• You will work with our backend and implementation teams to address synthesis, timing, DFT issues for the
ASIC implementation.
• You understand all design integration activities like Lint, CDC, Synthesis & ECO.
• You will define the verification and test plan, run regressions, reproduce, and debug functional and
performance bugs.
• You are responsible for the verification of various IPs/Sub IPs integrated to the top level SoC.
• Lastly: you will have an understanding of the design synthesis and fix timing issues for the Physical Design
team.
Requirements:
• Bachelor's degree or higher in Electrical Engineering
• 5+ years of experience as a Digital IC Design engineer.
• Proficience with EDA tools and design languages including Verilog.
• Experience with standard EDA tools like Candence and Mentor.
• You have experience in designing complex mixed-signal products containing analog building blocks and
microcontrollers.
• You have worked with RTL and ultra-low-power designs before. Good knowledge of digital design flow from
architecture design to sign-off
• You understand synthesis, static timing analysis, and netlist verifications
• You have some previous experience in digital backend flow for Floor Planning and Place & Route (PNR)
• You understand digital DFT/ECO flow
• You have strong programming and scripting skills: MATLAB, C/C++, Tcl
• Experience in setting up Power Distribution architecture, power intent specification and validation
methodology.
• Strong knowledge of clock domain crossing (CDC) techniques.
• Understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing
closure, STA, back annotation of parasitics, gate level simulation
• Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation
Perks and benefits:
• Given that they are a startup, we provide all our employees with Stock Appreciation Rights. You will be eligible to
financially profit from their success.
• We support you in your visa process if needed.
• Saving for your pension: we provide an extra 2% of your monthly base salary.
• 25 vacation days based on a 40-hour workweek.
• Work in a beautiful and modern office with all the necessary equipment you need to deliver a great job.
• Every quarter we organize fantastic social events, where they celebrate the success of by going out for a great
meal, playing VR games, going bowling, etc
Get in touch with Saphron@microtech-global.com at microTECH Global for more information on this role and
similar opportunities
Position: Permanant
Location: Delft, Netherlands
Salary Range: 60K – 75K EUR dependant on experience
Client Information:
Our client is on a mission to conquer the high-power consumption challenges in Global Navigation Satellite Systems
and IoT sensors. With a great team of over 25 individuals, scaling to 40 next year, hosting more than 12 nationalities,
we've achieved the impossible - the world's lowest power GNSS chipset. Now, we're on the verge of unleashing our
game-changing digital RF technology product, ready to flood the market with millions of annual shipments.
Responsibilities:
• You will work in our offices in Delft.
• You are responsible for ASIC verification, System Verilog, and UVM.
• You will be responsible for the simulation and verification of digital block implementation in RTL for various
functions, including control state machine digital processing (DSP), and multiple clock domain interface
management.
• You will be responsible for the post-layout simulation of complex mixed-signal SoC.
• As a Digital ASIC Verification engineer you will develop test benches and test cases for block-level functional
verification.
• You will work with our backend and implementation teams to address synthesis, timing, DFT issues for the
ASIC implementation.
• You understand all design integration activities like Lint, CDC, Synthesis & ECO.
• You will define the verification and test plan, run regressions, reproduce, and debug functional and
performance bugs.
• You are responsible for the verification of various IPs/Sub IPs integrated to the top level SoC.
• Lastly: you will have an understanding of the design synthesis and fix timing issues for the Physical Design
team.
Requirements:
• Bachelor's degree or higher in Electrical Engineering
• 5+ years of experience as a Digital IC Design engineer.
• Proficience with EDA tools and design languages including Verilog.
• Experience with standard EDA tools like Candence and Mentor.
• You have experience in designing complex mixed-signal products containing analog building blocks and
microcontrollers.
• You have worked with RTL and ultra-low-power designs before. Good knowledge of digital design flow from
architecture design to sign-off
• You understand synthesis, static timing analysis, and netlist verifications
• You have some previous experience in digital backend flow for Floor Planning and Place & Route (PNR)
• You understand digital DFT/ECO flow
• You have strong programming and scripting skills: MATLAB, C/C++, Tcl
• Experience in setting up Power Distribution architecture, power intent specification and validation
methodology.
• Strong knowledge of clock domain crossing (CDC) techniques.
• Understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing
closure, STA, back annotation of parasitics, gate level simulation
• Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation
Perks and benefits:
• Given that they are a startup, we provide all our employees with Stock Appreciation Rights. You will be eligible to
financially profit from their success.
• We support you in your visa process if needed.
• Saving for your pension: we provide an extra 2% of your monthly base salary.
• 25 vacation days based on a 40-hour workweek.
• Work in a beautiful and modern office with all the necessary equipment you need to deliver a great job.
• Every quarter we organize fantastic social events, where they celebrate the success of by going out for a great
meal, playing VR games, going bowling, etc
Get in touch with Saphron@microtech-global.com at microTECH Global for more information on this role and
similar opportunities
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| Digital IC Design / Verification: | Verification |
