SerDes System Architect
France - Grenoble
On-Site
Permanent
Principal Engineer – High-Speed SerDes System Architect
Location: Grenoble, France
Job Type : Permanent
Join a Leader in High-Speed Interconnect Innovation!
A global technology powerhouse is expanding its cutting-edge high-speed SerDes research team in Grenoble. Specializing in next-gen wireline communication (112Gbps+), AI infrastructures, and hyperscale data centers, this team drives breakthrough innovations in SerDes architectures, signaling, equalization, and FEC algorithms.
The Role:
- Lead research & innovation in high-speed wireline communication for future data centers & AI.
- Develop next-gen SerDes architectures (112Gbps+) and optimize equalization, modulation, and FEC.
- Collaborate with global R&D teams & top academic partners to drive industry advancements.
- Engage in IEEE, OIF standardization efforts and shape the future of high-speed interconnects.
- Mentor & guide PhDs, interns, and engineers in cutting-edge research.
Your Expertise:
- PhD/Master’s in EE, Signal Processing, or related field with 10+ years in SerDes system design.
- Deep knowledge of high-speed digital/analog circuits (Serializer, Deserializer) for 56G/112G NRZ & PAM.
- Expertise in signal integrity, equalization, synchronization, FEC & SerDes architectures.
- Familiarity with industry standards (IEEE 802.3, OIF-CEI, PCIe, DDR, InfiniBand).
- Proficiency in modeling & simulation tools (Python, MATLAB, Verilog-A, ADS).
This is your chance to push the boundaries of high-speed interconnect technology with a world-class research team.
Apply now and be part of the future of SerDes innovation!
Location: Grenoble, France
Job Type : Permanent
Join a Leader in High-Speed Interconnect Innovation!
A global technology powerhouse is expanding its cutting-edge high-speed SerDes research team in Grenoble. Specializing in next-gen wireline communication (112Gbps+), AI infrastructures, and hyperscale data centers, this team drives breakthrough innovations in SerDes architectures, signaling, equalization, and FEC algorithms.
The Role:
- Lead research & innovation in high-speed wireline communication for future data centers & AI.
- Develop next-gen SerDes architectures (112Gbps+) and optimize equalization, modulation, and FEC.
- Collaborate with global R&D teams & top academic partners to drive industry advancements.
- Engage in IEEE, OIF standardization efforts and shape the future of high-speed interconnects.
- Mentor & guide PhDs, interns, and engineers in cutting-edge research.
Your Expertise:
- PhD/Master’s in EE, Signal Processing, or related field with 10+ years in SerDes system design.
- Deep knowledge of high-speed digital/analog circuits (Serializer, Deserializer) for 56G/112G NRZ & PAM.
- Expertise in signal integrity, equalization, synchronization, FEC & SerDes architectures.
- Familiarity with industry standards (IEEE 802.3, OIF-CEI, PCIe, DDR, InfiniBand).
- Proficiency in modeling & simulation tools (Python, MATLAB, Verilog-A, ADS).
This is your chance to push the boundaries of high-speed interconnect technology with a world-class research team.
Apply now and be part of the future of SerDes innovation!
19003U9Q
| Analog / Mixed-Signal / RFIC: | High-Speed Design |
