Principal Chip Architect
Italy
On-Site, Hybrid, Remote
Permanent
Principal Chip Architect
Location: Remote, anywhere in Italy
About the Role
My Client is seeking a Principal Chip Architect to drive the definition, design, and optimization of next-generation AI processors. This is a key leadership position responsible for architecting high-performance digital subsystems, ensuring scalability, power efficiency, and seamless integration into cutting-edge AI hardware.
You will work closely with multidisciplinary teams, defining system specifications, leading microarchitecture design, and shaping the silicon roadmap. This is a high-impact role for an engineer passionate about innovation in compute, memory, and interconnect architectures.
Key Responsibilities
- Define chip and subsystem architectures for AI processing units.
- Develop scalable and power-efficient microarchitectures.
- Optimize performance, power, and area (PPA) across the design flow.
- Lead logical design efforts from concept to tape-out.
- Drive architectural validation, performance modeling, and verification.
- Collaborate with hardware, software, and verification teams to ensure seamless integration.
Required Skills & Experience
- 15+ years in chip architecture, digital design, or high-performance compute.
- Advanced degree in Electrical or Computer Engineering.
- Expertise in processor and accelerator architectures for AI/ML workloads.
- Deep knowledge of front-end ASIC design, including:
o SystemVerilog, synthesis, timing closure, and power optimization.
o Coherent interconnects, memory hierarchy, and dataflow architectures.
o SVA for formal property checking.
o Design for Testability (DFT) and verification methodologies.
o Strong proficiency in EDA tools, performance modeling, and scripting (Python, TCL).
o Experience in defining chip roadmaps and architectural trade-offs.
For more information, please get in touch.
Location: Remote, anywhere in Italy
About the Role
My Client is seeking a Principal Chip Architect to drive the definition, design, and optimization of next-generation AI processors. This is a key leadership position responsible for architecting high-performance digital subsystems, ensuring scalability, power efficiency, and seamless integration into cutting-edge AI hardware.
You will work closely with multidisciplinary teams, defining system specifications, leading microarchitecture design, and shaping the silicon roadmap. This is a high-impact role for an engineer passionate about innovation in compute, memory, and interconnect architectures.
Key Responsibilities
- Define chip and subsystem architectures for AI processing units.
- Develop scalable and power-efficient microarchitectures.
- Optimize performance, power, and area (PPA) across the design flow.
- Lead logical design efforts from concept to tape-out.
- Drive architectural validation, performance modeling, and verification.
- Collaborate with hardware, software, and verification teams to ensure seamless integration.
Required Skills & Experience
- 15+ years in chip architecture, digital design, or high-performance compute.
- Advanced degree in Electrical or Computer Engineering.
- Expertise in processor and accelerator architectures for AI/ML workloads.
- Deep knowledge of front-end ASIC design, including:
o SystemVerilog, synthesis, timing closure, and power optimization.
o Coherent interconnects, memory hierarchy, and dataflow architectures.
o SVA for formal property checking.
o Design for Testability (DFT) and verification methodologies.
o Strong proficiency in EDA tools, performance modeling, and scripting (Python, TCL).
o Experience in defining chip roadmaps and architectural trade-offs.
For more information, please get in touch.
19003U92
| Digital IC Design / Verification: | Digital IC Design |
