[CONTRACT] UVM Verification Engineer
Germany
Contract
Job Description
Job: UVM Verification Engineer
Location: Germany/Remote
Duration: 9 months:
Start Date: January 2025
For our client in Germany, we are currently looking for a UVM Verification Engineer. You will be working on block-level verification, integration verification of IPs and later top-level verification.
Experience
- Experienced in verification using SV-UVM
- Familiar with Cadence tool chain for verification and debug (familiar using Cadence VIPs would be a plus)
- Application expertise in I3C would be very much appreciated
- Application expertise in networking protocols like Ethernet and OTN would be a plus
- Expertise in using Python for modelling and verification would be a plus
Job: UVM Verification Engineer
Location: Germany/Remote
Duration: 9 months:
Start Date: January 2025
For our client in Germany, we are currently looking for a UVM Verification Engineer. You will be working on block-level verification, integration verification of IPs and later top-level verification.
Experience
- Experienced in verification using SV-UVM
- Familiar with Cadence tool chain for verification and debug (familiar using Cadence VIPs would be a plus)
- Application expertise in I3C would be very much appreciated
- Application expertise in networking protocols like Ethernet and OTN would be a plus
- Expertise in using Python for modelling and verification would be a plus
19003U3R
| Digital IC Design / Verification: | Verification |
