[CONTRACT] UVM Verification Engineer
Sweden - 111 21
Contract
Job Description
Job Title: UVM Verification Engineer
Duration: 6 months
Location: Sweden
Remote: Up to 100% available
Start: ASAP
Job Description
We are looking for an experienced verification engineer to lead innovation in the ever-evolving world of telecommunications.
As a member of the team, the candidate will be instrumental in shaping the 5G and 6G waves. Experience and insight will play a pivotal role in ensuring the delivery of high-quality IPs that shape the future of global connectivity. Expertise will be critical in turning game-changing ideas into real-world solutions that will shape the future of connectivity while being part of a culture that thrives on creativity, collaboration, and making a real-world impact.
Responsibilities
- Develop a comprehensive verification planning, including specifications.
- Architect and enhance state-of-the-art verification environments.
- Implement and maintain UVCs, ensuring every corner of the design is verified.
- Drive both random and directed testing strategies to uncover hidden bugs.
- Leverage advanced coverage techniques to ensure top-tier verification completeness.
- Champion continuous improvement in product quality, efficiency, and workflows.
Requirements
- Expertise in ASIC or FPGA verification at IP, sub-system, and chip levels, using SystemVerilog UVM.
- Hands On experience designing UVM test environments and driving coverage closure
- An insatiable curiosity, ready to learn something new daily and apply it to make a real difference.
- Creative problem-solving skills—you see challenges as opportunities for innovation.
- A collaborative spirit and the ability to thrive independently, with exceptional communication skills.
- A results-oriented mindset with a passion for continuous improvement, always seeking more innovative, faster solutions.
- A Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Job Title: UVM Verification Engineer
Duration: 6 months
Location: Sweden
Remote: Up to 100% available
Start: ASAP
Job Description
We are looking for an experienced verification engineer to lead innovation in the ever-evolving world of telecommunications.
As a member of the team, the candidate will be instrumental in shaping the 5G and 6G waves. Experience and insight will play a pivotal role in ensuring the delivery of high-quality IPs that shape the future of global connectivity. Expertise will be critical in turning game-changing ideas into real-world solutions that will shape the future of connectivity while being part of a culture that thrives on creativity, collaboration, and making a real-world impact.
Responsibilities
- Develop a comprehensive verification planning, including specifications.
- Architect and enhance state-of-the-art verification environments.
- Implement and maintain UVCs, ensuring every corner of the design is verified.
- Drive both random and directed testing strategies to uncover hidden bugs.
- Leverage advanced coverage techniques to ensure top-tier verification completeness.
- Champion continuous improvement in product quality, efficiency, and workflows.
Requirements
- Expertise in ASIC or FPGA verification at IP, sub-system, and chip levels, using SystemVerilog UVM.
- Hands On experience designing UVM test environments and driving coverage closure
- An insatiable curiosity, ready to learn something new daily and apply it to make a real difference.
- Creative problem-solving skills—you see challenges as opportunities for innovation.
- A collaborative spirit and the ability to thrive independently, with exceptional communication skills.
- A results-oriented mindset with a passion for continuous improvement, always seeking more innovative, faster solutions.
- A Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
19003U3L
| Digital IC Design / Verification: | Verification |
