Principal Digital Architect
France - France
Permanent
Job Title: Principal Digital Architect
Position: NoC SoC Cache Coherency Architecture
Location: Biot, France
Salary Range: 100K-130K EUR per annum
Client Information:
Connect and integrate today’s system-on-chips (SoCs) to fuel modern innovation.
As a Cache Coherency Architect, you will be an important contributor, defining and optimizing cache coherency solutions within my client’s advanced IP portfolio.
Your primary focus will be on developing cutting-edge cache coherent interconnect IP and ensuring seamless integration with other NoC interconnects, and system IP to support efficient and coherent communication between multiple processor and accelerator cores and functional units.
You will collaborate closely with hardware designers, verification engineers, software developers, and other stakeholders to create high-performance, power-efficient, and reliable NoC IP solutions.
Responsibilities:
Cache Coherency Architecture:
•Evaluate industry-standard cache coherency protocols and maintain/improve proprietary protocols within highly configurable NoC IP.
•Develop scalable cache coherency architectures that align with the overall System-on-a-Chip (SoC) design.
•Analyze customer requirements for cache-coherent system architectures, including partitioning large designs into chiplets using die-to-die and chip-to-chip architectures based on standards like CXL, UCIe, PCIe.
•Set performance goals (PPA) for configurable IP.
NoC Integration:
•Collaborate with SoC design teams to ensure seamless integration of cache coherency into the SoC architecture.
•Optimize Cache Coherency Architecture & Architecture within the NoC to minimize latency & improve bandwidth.
Performance and Power Optimization:
•Identify performance bottlenecks and power consumption issues; propose and implement solutions to enhance efficiency.
•Work with hardware and software teams to verify and optimize cache coherency mechanisms.
Protocol Verification:
•Support verification teams in developing strategies to ensure the correctness and robustness of cache coherency protocols.
•Assist emulation teams in testing and debugging cache coherency behaviors for functional accuracy and performance.
Cross-Functional Collaboration:
•Work with marketing and sales teams to gather customer feedback and understand market/product requirements.
•Collaborate with hardware design, software development, and system architecture teams to address their needs and concerns.
•Provide technical support to the FAE team for seamless integration of products into customer designs.
Industry Research and Innovation:
•Stay updated on advancements in cache coherency and NoC technologies.
•Evaluate emerging methodologies, standards, and trends to enhance NoC IP offerings.
Documentation and Communication:
•Prepare detailed technical documentation, including architecture specifications, design guidelines, and white papers.
•Communicate complex technical concepts effectively to both technical and non-technical stakeholders.
Requirements:
•Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
•Proven experience as a Cache Coherency Architect, Design Engineer, or similar role focused on NoC IP development.
•In-depth knowledge of SoC and NoC architecture, cache coherency protocols, and memory hierarchy.
•Strong understanding of cache hierarchies and their interaction with NoC interconnects.
•Experience in cache coherency verification and validation techniques.
•Familiarity with hardware description languages (HDLs) and SoC design tools.
•Strong analytical and problem-solving skills with a strategic mindset.
•Excellent communication and collaboration skills to work effectively with diverse teams and stakeholders.
•Experience with HDLs and design tools used in NoC IP development, or prior experience designing coherent systems is a plus.
Get in touch with Jessica@microtech-global.com for
Position: NoC SoC Cache Coherency Architecture
Location: Biot, France
Salary Range: 100K-130K EUR per annum
Client Information:
Connect and integrate today’s system-on-chips (SoCs) to fuel modern innovation.
As a Cache Coherency Architect, you will be an important contributor, defining and optimizing cache coherency solutions within my client’s advanced IP portfolio.
Your primary focus will be on developing cutting-edge cache coherent interconnect IP and ensuring seamless integration with other NoC interconnects, and system IP to support efficient and coherent communication between multiple processor and accelerator cores and functional units.
You will collaborate closely with hardware designers, verification engineers, software developers, and other stakeholders to create high-performance, power-efficient, and reliable NoC IP solutions.
Responsibilities:
Cache Coherency Architecture:
•Evaluate industry-standard cache coherency protocols and maintain/improve proprietary protocols within highly configurable NoC IP.
•Develop scalable cache coherency architectures that align with the overall System-on-a-Chip (SoC) design.
•Analyze customer requirements for cache-coherent system architectures, including partitioning large designs into chiplets using die-to-die and chip-to-chip architectures based on standards like CXL, UCIe, PCIe.
•Set performance goals (PPA) for configurable IP.
NoC Integration:
•Collaborate with SoC design teams to ensure seamless integration of cache coherency into the SoC architecture.
•Optimize Cache Coherency Architecture & Architecture within the NoC to minimize latency & improve bandwidth.
Performance and Power Optimization:
•Identify performance bottlenecks and power consumption issues; propose and implement solutions to enhance efficiency.
•Work with hardware and software teams to verify and optimize cache coherency mechanisms.
Protocol Verification:
•Support verification teams in developing strategies to ensure the correctness and robustness of cache coherency protocols.
•Assist emulation teams in testing and debugging cache coherency behaviors for functional accuracy and performance.
Cross-Functional Collaboration:
•Work with marketing and sales teams to gather customer feedback and understand market/product requirements.
•Collaborate with hardware design, software development, and system architecture teams to address their needs and concerns.
•Provide technical support to the FAE team for seamless integration of products into customer designs.
Industry Research and Innovation:
•Stay updated on advancements in cache coherency and NoC technologies.
•Evaluate emerging methodologies, standards, and trends to enhance NoC IP offerings.
Documentation and Communication:
•Prepare detailed technical documentation, including architecture specifications, design guidelines, and white papers.
•Communicate complex technical concepts effectively to both technical and non-technical stakeholders.
Requirements:
•Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
•Proven experience as a Cache Coherency Architect, Design Engineer, or similar role focused on NoC IP development.
•In-depth knowledge of SoC and NoC architecture, cache coherency protocols, and memory hierarchy.
•Strong understanding of cache hierarchies and their interaction with NoC interconnects.
•Experience in cache coherency verification and validation techniques.
•Familiarity with hardware description languages (HDLs) and SoC design tools.
•Strong analytical and problem-solving skills with a strategic mindset.
•Excellent communication and collaboration skills to work effectively with diverse teams and stakeholders.
•Experience with HDLs and design tools used in NoC IP development, or prior experience designing coherent systems is a plus.
Get in touch with Jessica@microtech-global.com for
19003U1M
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