[CONTRACT] UVM Verification Engineer
France - Sophia-Antipolis, Cedex
Contract
Job Description
Job Title: UVM Verification Engineer
Job Type: Contract
Duration: Initial contract to end of year (2024) - further extension to end of 2025
Location: Remote, France
Start: ASAP
We currently require a UVM Verification Engineer for a client in France. Joining their Digital Verification team you will be working extensively within their UVM environment to assist on their High Speed SOCs.
For this, our client requires knowledge and experience in the following areas:
- Extensive knowledge of UVM verification
- SystemVerilog
- Automated framework implementation
- Extensive experience in ASIC verification
- Knowledge of high speed interfaces, specifically Ethernet or the like
- SoC Verification preferred but IP is okay
For more information on the position and the company, please contact us with an updated CV, availability and required rate.
Job Title: UVM Verification Engineer
Job Type: Contract
Duration: Initial contract to end of year (2024) - further extension to end of 2025
Location: Remote, France
Start: ASAP
We currently require a UVM Verification Engineer for a client in France. Joining their Digital Verification team you will be working extensively within their UVM environment to assist on their High Speed SOCs.
For this, our client requires knowledge and experience in the following areas:
- Extensive knowledge of UVM verification
- SystemVerilog
- Automated framework implementation
- Extensive experience in ASIC verification
- Knowledge of high speed interfaces, specifically Ethernet or the like
- SoC Verification preferred but IP is okay
For more information on the position and the company, please contact us with an updated CV, availability and required rate.
19003U0X
| Digital IC Design / Verification: | Verification |
